A delay locked loop (DLL), is used in many cases for delaying a clock signal in integrated semiconductor circuits. Such a control loop is used in digitally operating circuits in order to bring clock signals into an identical phase angle.
This is the case in synchronously operated integrated semiconductor memories, e.g., in which data values are valid both upon the rising edge and upon the falling edge of a clock signal that validates the data. The semiconductor memories are referred to as double data rate synchronous dynamic random access memories, (DDR SDRAM). The DDR SDRAM includes a delay locked loop that provides data synchronously with an input clock signal for the component. From the input clock signal, it is necessary to generate an internal delayed signal that has a phase angle that makes it possible to provide data synchronously with the clock signal at the device terminals of the DDR SDRAM. The internal delay locked loop has to account for the internal signal propagation times.
A customary delay locked loop compares the input clock signal for the device with the delayed signal, generated by the delay locked loop, and sets the delay in a delay chain such that the phase difference is as far as possible regulated to zero. What is particularly important in this case is that the delayed signal generated is as stable and free of jitter as possible.
Typical operating frequencies for DDR SDRAMs are 500 megahertz. Known delay locked loops have a delay chain, a phase detector and a control unit and have the disadvantage that a relatively large number of clock cycles are required before the delay time of the delay chain is set. Since a DDR SDRAM can be used at different frequencies, the delay locked loop has to be designed flexibly such that a satisfactory synchronization of the phase angles is achieved for both the lower frequency values and the upper frequency values for which the DDR SDRAM is specified.